This invention relates to circuitry for encoding binary signals that are typically of the "non-return-to-zero" (NRZ) type into signals that are of the "code mark inversion" (CMI) type.
The CMI code was first introduced in a published contribution (proposal No. 14) to the International Telegraph and Telephone Consultative Committee (C.C.I.T.T.), entitled "An equipment interface code for operating rates above 100 M bits/s", dated Feb. 1974. This code is primarily used as an interface code for transferring binary information between different points within terminal stations for digital communication, e.g., within a telephone exchange station. The underlying principle of the CMI code has been known since the publication by W. Neu, in Bull. Sev., 51, 1960, on pages 978-980. In the CMI code, binary 0 is represented by both amplitude levels being attained consecutively, each for a half a unit time interval, and binary 1 is represented by either of the amplitude levels being attained for one full unit time interval, the level alternating for successive binary 1's.
Another important characteristic of this code is that all negative transistions occur at a time coincident with the start of a binary unit time interval which allows the clock information to be recovered at the receiving end, thus no extra clock transmission line is needed.
A simple design of a CMI encoder is shown in British Pat. No. 1,251,878. With this and other previously known encoding concepts for CMI codes the signals from the signal channels have to be closely timed relative to each other, as the timing of the output signals is affected by any signal propagation delays in the logic and storage elements as well as by any time shifts between the clock pulses and data signals. Otherwise, either glitches which affect the logic information or pulse narrowing which affects the clock recovery will occur at the output logic gates of the signal channels.
A major characteristic of CMI encoded signals is that they have no DC component since each of the two logic levels of the NRZ-signals is encoded by a pulse pattern which has the same amount of upper levels as lower levels. As this method of encoding can occur in different manners for CMI code related signals such as NRZ signals, (see e.g., U.S. Pat. No. 3,953,673), reference will be made herein to CMI code related signals generally. However, for the purpose of simplicity, the further explanation will start from a single one out of the many possible code definitions, with the understanding that a subsequent encoder could easily be modified for encoding any of the CMI code related signals without departing from the inventive concept.
FIG. 2 of the above mentioned prepublished proposal to the C.C.I.T.T. discloses an encoding circuit for implementing the CMI code. This known encoding circuit includes a signal channel with flipflop and gating circuit for deriving from an NRZ input signal and from a clock input pulse a signal representing a logical "1" to be applied to one input of an AND-gate. A clock channel is connected to an inverting input of another AND-gate to establish the logical "0". Furthermore, there is a control channel for transferring the input NRZ signals to second inputs of the ANDgates in order to enable the one and to disable the other of these gates depending on the actual binary value of the NRZ signals. The outputs of both AND-gates are connected to an OR-gate for delivering the CMI encoded signal.
With this known encoding concept, the signals from the three signal channels should be closely timed relative to each other as the CMI output signals are composed of waveform sections from the clock channel for the logical "0" and from the signal channel for the logical "1." Otherwise the trailing signal edges in the CMI waveform for the logical "1" may be shifted in time with regard to the trailing signal edges derived from the clock channel. Furthermore, the flipflop and gating circuitry of the signal channel introduce delays in the signal flow relative to the signals in the other two channels. Thus either glitches which affect the logic information, or pulse narrowing which affects the clock recovery, will occur at the output of the logic gates which combine the signals from these three signal channels.